Nehalem (Intel Core i7) in context
Introduction: ritchan is a Malaysian attending college in Germany who has been following computers for quite a while now. Although he has no interest in files commonly released by ‘the scene’, he finds other things to download, mostly Japan-related, and as a result knows, at least, how to get the files.
UPDATE: RealWorldTech has an in-depth article on the little differences between the Core 2 and Athlon 64 here. It’s worth noting that Intel invested a lot into branch prediction, especially during the Pentium IV days.
Intel has been using a bus layout with GTL since the Pentium Pro. That’s 1995, folks. Since then, it’s been enhanced - GTL+ with the Pentium III, AGTL with the Pentium 4 and beyond - but its days were numbered when AMD integrated a memory controller onto their Athlon 64 CPUs (hereby referred to as Hammer), thus giving Hammer a direct, low latency connection to RAM. In contrast, Intel CPUs go through a bus to communicate with the northbridge, which includes the memory controller, to access RAM. With advanced prefetching to hide latency (see Core 2). When there are multiple CPUs sharing the bus, for example a multi-socket system with 4 quad-core Xeons for example, the bus becomes a limiting factor. AMD still sells rather well in the supercomputing markets because of this.
For instance, let’s talk about AMD’s Athlon processor. With a design team headed by Dirk Meyer, co-architect of the Alpha 21064 and 21264 processors (famous for running at 500-600MHz at a time when Pentium IIs were available at only 333MHz), AMD was finally able to produce a processor that not only performed as well as Intel’s offerings (then the Pentium III), but also exceeded it in clock rates. The Athlon’s FSB transferred two bits per Hertz in comparison to GTL, which only transferred 1 bit per Hertz. Just by this, Athlon had double the memory bandwidth of Pentium III, had a stronger floating point unit (which really helped in games), and higher clock speeds. Intel also experienced a number of difficulties in bringing the Pentium III up to snuff (initial samples of the Pentium III 1.13GHz, for example, threw errors while compiling the Linux kernel).
The Athlon XP was introduced and furthered AMD’s lead. The Pentium IV, with its AGTL signalling, managed to transfer four bits per Hertz, but stumbled thanks to Intel’s decisions (SDRAM paired with AGTL = underutilized bus by a factor of 4; RDRAM was expensive, nobody cared). It was not competitive until Intel’s FSB hit 133×4=533 effective MHz with the Pentium IV 2.53GHz processor. Then AMD was in a bit of a tight spot, but not that tight.
The Athlon 64 (codename Sledgehammer), when it first came out, was revolutionary. At a high level, you could say it really was just an Athlon XP with a memory controller tacked on (of course, there were many other improvements) but everybody else was just too busy buying them, they outperformed Intel’s Pentium IV Extreme ‘Emergency’ Editions even with a 800MHz FSB and were cheaper in any case. With its integrated memory controller, it could access RAM faster than ever; it now supported SSE2; a slightly deeper pipeline with SoI process meant higher clock speeds achievable compared to the Athlon XP, and most importantly, the 64 wasn’t just for show. It was the first 64bit x86 processor. This meant that huge corporations could now work with more than 4GBs of RAM - I’ve heard that oil drilling calculations need a lot of RAM. This also meant that AMD had a chance to modernize the aging x86 ISA (now 30 years old) by adding 8 more registers - I read on RealWorldTech that the x86 was so register-starved that it would be the only ISA to receive a speed boost as a direct result of having 16 registers instead of 8. The Pentium IV sat in Hammer’s shadow for the rest of its life until Core 2 came around. Now the tables have changed - Core 2, an ultra-wide implementation of the Pentium III Tualatin (which in turn was a polished Pentium II, which in turn was a Pentium Pro with better 16bit app performance), was just fundamentally faster, no dirty tricks here. It even managed to get to memory faster than the Athlon 64, thanks to its very robust prefetching algorithms (as you can guess, prefetching fetches data which the processor thinks it will need in the future). SSE4 further widened the gap - on some benchmarks you can see Intel’s dual core E8200/E8400s outperforming quad core AMD Phenom X4s by a healthy margin. Clock for clock, Intel’s Core 2 CPUs were faster - and as soon as the Core 2 architecture went 45nm, Intel managed a healthy clock frequency gain over AMD’s Phenom CPUs.
Remember how the Athlon 64 was revolutionary? Now that’s what Nehalem is all about, except Intel’s already leading by a huge performance margin (it had 45nm CPUs out for a while now, while AMD is still struggling). The execution units are the same, except that it can reorder up to 128 instructions at once, it can macrofuse x86 instructions in 64bit mode (the Core 2 couldn’t), it has a generous 8MB L3 cache (dear AMD lagging even on that front), and it doesn’t have to go through a slow FSB to get to memory now. Oh, and it also does simultaneous multithreading (better known as HyperThreading which generally improves performance - generally) so a quad-core Nehalem will look like 8 CPUs to the operating system. Unlike the Hammer, Nehalem will also introduce a few new SSE instructions (SSE 4.1).
Well, but just how much faster is the Nehalem then? Anandtech has a look. Clock for clock, Nehalem is faster than the already formidable (at least to AMD) Core 2 CPUs, to the extent that a 3.2GHz Core 2 Quad gets consistently outgunned by the 2.66GHz Nehalem.
Of course, you probably won’t be able to afford the high end triple-channel DDR3 versions. Thus the dual-channel DDR3 CPUS that will be released in 2009 - I’m not sure about the names of these derivatives (Nehalem is the umbrella code name for this lineup), but you can always look it up on Wikipedia. If nothing else, the introduction of the high-end Nehalem later this year will certainly drive Core 2 prices down.
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